The present invention relates generally to a parallel decimation circuit for decimating waveform data on an oscilloscope.
Traditionally, digital storage oscilloscopes (DSOs) capture an electrical signal (waveform) and allow the user to view a trace of the captured signal in a time (x-axis) versus amplitude (y-axis) display. This is done by digitally sampling the waveform, thereby generating a number of samples. Current DSOs can acquire data at a rate of 109 samples per second. At this rate, a gigabyte of storage is needed to cover one second of data. Storing this amount of data quickly exceeds the capacity of even the largest DSO memories. Furthermore, display screens lack the resolution to display this amount of data. Realistically, a display needs only about 1000 data points to produce a suitable trace of the waveform. Thus, to display a one second trace, almost 106 samples are discarded between each of the display points.
For these reasons, DSOs commonly reduce the number of samples through a reduction operation called decimation. The decimation operation can be performed during acquisition of the waveform, storage of the samples, processing of the data, and/or rendering of the display. For most of these stages the decimation operation may be performed in software. However, during acquisition the software implementation is too slow to keep pace with the incoming data.